1. Field of the Invention
This invention relates to electrostatic discharge protection of integrated circuit devices, and more particularly, to an electrostatic discharge protection device that is decoupled from an integrated circuit device.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Integrated circuit devices such as common silicon integrated circuits typically have delicate construction that is susceptible to damage by voltage spikes such as voltage spikes caused by electrostatic discharge. Such voltage spikes may occur in various situations such as during manufacturing of an integrated circuit, handling of the integrated circuit after packaging, and handling of a board after assembly such as during use of the board. There are a number of models that may be used to describe such damage to an integrated circuit device. For example, the human body model (HBM) describes a voltage spike condition caused by electrostatic discharge from a human body to an integrated circuit device. For an integrated circuit device to be commercially viable, it has to be protected against this condition except under special circumstances such as when manufacturers and customers specifically agree on the lack of such protection. This agreed upon lack of HBM protection is necessary because lack of this protection may require special handling of the integrated circuit device that complicates logistics, increases handling costs, and increases the probability of damaging the device.
To protect against electrostatic discharge, a silicon die typically includes protection circuitry (or an xe2x80x9cHBM structurexe2x80x9d) that will divert or otherwise dissipate the energy caused by a voltage spike. In this manner, the core logic circuitry of the die may not be damaged by the voltage spike. An HBM structure is the xe2x80x9cfirst line of defensexe2x80x9d for input/output (I/O) cells. Therefore, the structure is integrated into the die and is adjacent to or outside of the I/O cells through which the die interacts with the external environment (i.e., through device pins).
Development of the HBM structure, however, is usually difficult as development hinges upon understanding of process technology and how its various underlying factors interact so that an adequate structure can be developed. An adequate HBM structure also has to react fast to a voltage spike (i.e., it has to react faster than the internal circuitry) to be effective. In addition, HBM structures have to dissipate relatively large amounts of energy. On the other hand, an HBM structure cannot present an undue burden to I/O cells in areas such as current consumption and capacitance as these factors affect the performance of the device.
There are several disadvantages of currently available HBM structures. For example, the electrical design of an HBM structure is difficult to develop correctly without some experimentation due to lack of means of accurate simulations. In particular, the electrical design of an HBM structure may be difficult to develop if a new process is being used for the die. In addition, the practice of integrating an HBM structure into the base die, where the logic and regular I/O circuitry reside, may cause revision of the entire die if the HBM structure is inadequately designed. Such revision may be especially problematic if the revision of the die is solely required due to the HBM structure because the expensive tape-out of the die adds no value to the performance or functionality of the device. Additionally, while an optimal HBM structure is desired for a device, the fact that its revision causes expensive revision of the entire die and re-tape-out discourages experimentation of HBM structures thereby hindering HBM structure design. Furthermore, an HBM structure may enlarge the size of the integrated circuit die thereby increasing die cost and making a die revision for any reason more expensive than it would be without the HBM structure. Revision of an HBM structure if an existing one is inadequate requires re-layout of the device that often goes beyond the structure itself. For example, such revision may affect the I/O cell layout of the device. This revision and/or re-layout may delay product launch and increase the product development time and cost.
Accordingly, it may be advantageous to develop an HBM structure that allows revision of the HBM structure without revision of the entire die and/or re-tape-out or re-layout of the entire device, allows less problematic and less expensive revision such that better HBM structures may be developed, reduces the size of the die thereby reducing cost of the die and revision of the die for any reason, reduces product development time and costs, and allows reuse of the HBM structure for various integrated circuits.
The problems outlined above may be in large part addressed by an embodiment of a semiconductor device including an integrated circuit and an HBM structure formed on separate semiconductor substrates. Various embodiments described herein may reduce, and even eliminate, problems such as HBM structure-induced integrated circuit latch-up, integrated circuit partitioning problems due to the HBM structure, and product delay due to HBM structure development. In addition, if an integrated circuit and an HBM structure are formed on different semiconductor substrates, then the die size of the integrated circuit may be reduced thereby reducing integrated circuit manufacturing costs. There are several additional advantages to the various embodiments as described herein.
In an embodiment, the integrated circuit may be formed on a first semiconductor substrate. The HBM structure may be formed on a second semiconductor substrate. The integrated circuit may include, for example, logic circuitry, charged-device model (CDM) structures, other circuitry typically included in an application specific integrated circuit (ASIC), and optionally portions of the input/output cells of the integrated circuit. The HBM structure may include input or output or input/output circuitry coupled to the integrated circuit. In an embodiment, the HBM structure may also include input/output cells of the integrated circuit. The input or output or input/output circuitry may be included in the input/output cells. The HBM structure may also include protection structures coupled to the input or output or input/output circuitry. The semiconductor device may also include a package substrate to which the first and second semiconductor substrates may be connected directly or through a pair of back to back diodes. The protection structures of the HBM structure may be further coupled to signal traces of the package substrate. In this manner, the protection structures may be configured to protect the input/output cells of the integrated circuit from electrostatic discharge that may be conducted through the signal traces.
In an embodiment, the input or output or input/output circuitry of the HBM structure may be coupled to the integrated circuit by wire bonding. In an alternative embodiment, the input or output or input/output circuitry of the HBM structure and the integrated circuit may be coupled to a signal trace within the package substrate by wire bonding. In a further embodiment, the input or output or input/output circuitry of the HBM structure and the integrated circuit may be connected to a signal trace within the package substrate by solder bumps. According to yet another embodiment, the semiconductor device may also include two or more HBM structures. Each of the two or more HBM structures may include a portion of the input or output or input/output circuitry and protection structures coupled to the portion of the input or output or input/output circuitry.
Latch-up and other problems associated with the HBM structure may be reduced, and even eliminated, by an HBM structure de-coupled from the integrated circuit. For example, when the HBM structure is integrated into the integrated circuit as is currently done, the HBM structure and the integrated circuit are formed on a common substrate. Typically, HBM structures are large in size. In this manner, a large number of minority carriers may be injected from the HBM structure to the integrated circuit. Such carrier flow may cause latch-up in the integrated circuit in the event of a sudden large current flow during device operation. Currently, to reduce latch-up of the integrated circuit, the input/output portion of the HBM structure may be isolated from the integrated circuit by inserting complex guard ring structures between the HBM portion and the integrated circuits. Carriers, however, may still flow from the HBM structure to the integrated circuit across the common substrate. In embodiments as described herein, however, minority carrier flow from the HBM structure into the integrated circuit may be greatly reduced because the HBM structure and the integrated circuit are formed on different semiconductor substrates. Therefore, latch-up of the integrated circuit may be reduced due to the limited carrier flow from the HBM structure into the integrated circuit.
In addition, different manufacturing processes may be used to form the HBM structure and the integrated circuit because the HBM structure and the integrated circuit are not formed on the same semiconductor substrate. In this manner, the HBM structure may be formed using a processing technology different from that used to form the integrated circuit. For example, the integrated circuit may be formed using advanced processing technology with relatively fine line width and a relatively large number of layers of metal. In contrast, the HBM structure, due to simpler design, may be formed using more traditional technology with larger line width and fewer metal layers. As such, devices of the integrated circuit may have substantially different average critical dimensions than devices of the HBM structure. In addition, the HBM structure may have a different number of layers than the integrated circuit. Therefore, forming the HBM structure with more traditional technology may lower overall costs of the device.
Another embodiment relates to a semiconductor device that also includes an integrated circuit and an HBM structure formed on different semiconductor substrates. The HBM structure may be formed on a second semiconductor substrate. In this embodiment, the integrated circuit may be formed on a first semiconductor substrate. The integrated circuit may include input or output or input/output structures spaced across an area of the integrated circuit. The area may include a central portion of the integrated circuit and a peripheral portion of the integrated circuit. In an embodiment, the input or output or input/output structures may not be surrounded by guard rings. Guard rings may include a continuous ring of n-diffusion in an n-well connected to VDD and a ring of p-diffusion in a p-well connected to VSS to collect minority carriers thereby reducing flow of the carriers into a portion of the substrate occupied by the integrated circuit. Guard rings, however, require a relatively large area of the substrate and increase the difficulty of designing an integrated circuit having input/output cells not only at the periphery of the integrated circuit but also proximate a central portion of the integrated circuit. Therefore, eliminating such guard rings reduces the difficulty of silicon partitioning.
Moreover, as the speed of an integrated circuit increases, wire bonding and placing inputs or outputs or input/outputs proximate the periphery of the integrated circuit, but not proximate the central portion of the integrated circuit, may not be adequate for such integrated circuits. For example, isolating the HBM structure to protect the integrated circuit by limiting the input or output or input/output locations within the integrated circuit may result in inefficient use of die space and reduced performance of such high speed integrated circuits. De-coupling the HBM structure and the integrated circuit may, therefore, reduce, and even eliminate, such concerns.
The HBM structure may include input or output or input/output circuitry coupled to the input or output or input/output structures of the integrated circuit. In an embodiment, the input or output or input/output structures may be self-aligned to the input or output or input/output circuitry. For example, the semiconductor device may include a package substrate to which the first and second semiconductor substrates may be connected. The first and second semiconductor substrates may be connected to the package substrate in a flip chip stacked ball grid array configuration. Therefore, in such an embodiment, input or output or input/output structures may be spaced across the area of the integrated circuit at convenient positions and at positions that may increase circuit performance without constructing complicated tapping to isolate the HBM structure from the integrated circuit. In addition, the HBM structure may include protection structures coupled to the input or output or input/output circuitry.
A further embodiment relates to a method for developing a design for an HBM structure. The method may include forming an HBM structure having an initial HBM design on a first semiconductor substrate. The method may also include coupling the first semiconductor substrate to a package substrate and coupling the HBM structure to an integrated circuit coupled to the package substrate. The integrated circuit may be formed on a second semiconductor substrate. In addition, the method may include testing the HBM structure. The method may further include altering the initial HBM design based on the testing.
In an embodiment, the method may include forming an additional HBM structure having the altered initial design without altering a design of the integrated circuit. The method may also include forming an additional HBM structure having the altered initial design without altering manufacturing of the integrated circuit. In an embodiment, the method may include altering a design of the integrated circuit without further altering the initial design of the HBM structure. Altering an HBM structure die does not require altering an integrated circuit die and vice versa because the die are formed on separate semiconductor substrates. Altering one of the die, instead of both die, will reduce re-layout time and costs associated with re-layout of both die.
The method may also include forming an additional HBM structure having the altered initial design without manufacturing an additional integrated circuit Therefore, such embodiments may reduce the costs of manufacturing another integrated circuit on the same die as the additional HBM structure. Furthermore, because the HBM structure may be manufactured separately from the integrated circuit, the HBM structure may be used to protect other integrated circuits and perhaps at a reduced cost. In another embodiment, the method may further include using the HBM structure until an additional HBM structure having the altered initial design can be formed and coupled to the integrated circuit. In this manner, if the HBM structure will sufficiently protect a new integrated circuit product, the HBM structure may be used as an interim solution for the new integrated circuit product while an optimal HBM structure is being developed for the new product thereby reducing product delay. As such, the new product may be shipped as an HBM protected device while the development of the HBM structure continues. Such a method may also be used for integrated circuits having an integrated HBM structure.
Additional HBM structures may be experimentally tested as described herein. ESD structures such as an HBM structure are often difficult to develop without some experimentation. For example, an adequate HBM structure is often difficult to determine prior to experimentation because an adequate design of the structure often requires process technology characterization, which may be difficult to obtain without taping out the integrated circuit. Determining an adequate HBM structure may be particularly difficult if the integrated circuit process technology includes new processes and/or technologies. The development of such structures also tends to be performed proximate the end of the product design cycle. Therefore, developing an HBM structure separately from an integrated circuit may reduce the development time for the HBM structure thereby speeding product launch.